MAD-65 is designed to be built by one person on a desk. Everything is through-hole, every part is in production and orderable today, and there is no FPGA, no BGA, and nothing that needs a reflow oven or a hot-air station.
Status: design complete, boards not yet manufactured. The full system is specified and verified in simulation, both firmware ROMs are written and working, and the CPLD logic is done. PCB layout is in progress. Gerbers, ordering instructions and a build guide will appear here when the first boards have been assembled and tested in the flesh.
Until then the documentation below is complete and accurate, and the whole machine can be run in simulation. If you want to follow along, this is a good time to read rather than to order parts.
Three boards that cable together:
| Board | ICs | What it does |
|---|---|---|
| PCB1: CPU | 10 | Runs the game. 65C02, 64 kB RAM, 16 kB ROM, cartridge slot, three sound chips, two joystick ports, stereo audio out. |
| PCB2: GPU | 16 | Draws the picture. A second 65C02, 128 kB of double-buffered video RAM, and the video engine that generates the SVGA signal. |
| PCB3: shared RAM | 7 | The letterbox between the two CPUs. Two small SRAMs whose ownership swaps every frame, so neither processor ever waits for the other. |
Thirty-three chips in total. The logic that would traditionally take dozens of 74-series packages is folded into five ATF1508AS CPLDs, which you program yourself over JTAG with a USB-Blaster clone. The source for all five is plain SystemVerilog and is published in full.
You do not need to know Verilog, VHDL, or 6502 assembly to build one. You need those only to change it.
Four design decisions are what make the machine what it is, and each is written up in full in the documentation:
Both processors share one crystal. Two 2 kB SRAMs swap owners at every vertical sync, so each CPU has exclusive use of one chip for the whole frame. No bus arbiter, no wait states, no contention — just a clean handover between bus cycles. Architecture doc →
A frame moves down a line of three stations, handed on at every VSYNC. The CPU writes a list of drawing commands. VSYNC. The GPU executes that list into a video buffer. VSYNC. The video circuit scans the buffer onto the screen and, on every second scanline, overwrites it with the background layer — so the moment the frame ends, that buffer is already wiped and primed for the GPU's next pass. Clearing the screen, which on most machines eats a large part of the frame budget, is done by neither processor: it falls out of scanout for free. Three frames are always in flight, no stage ever waits for another, and the cost is a fixed two-frame lag between decision and photons. Architecture doc →
The video circuit copies a background layer into the visible framebuffer during the spare half of every doubled scanline. The GPU never spends a cycle redrawing static scenery. Video circuit doc →
An EPROM cannot keep up with a 14.3 MHz 65C02, so both CPUs copy their firmware into RAM at boot and run it from there at full speed. The slow ROM reads happen once, and never again. Decoder doc →
| Processors | 2× WDC W65C02S @ 14.318 MHz (shared NTSC crystal) |
|---|---|
| Display | 400×300 logical, 1 bit per pixel |
| Output | 800×600 SVGA @ 60.3 Hz, 20 MHz pixel clock, VGA connector |
| Video RAM | 128 kB (4× CY7C199), double-buffered |
| Main RAM | 64 kB per CPU |
| Firmware | 16 kB ROM per CPU, shadowed into RAM at boot |
| Shared RAM | 2× 2 kB, swapped each frame |
| Sound | 2× SN76489 PSG (6 tone + 2 noise) and 1× YM2413 OPLL (9 FM channels), all at 3.58 MHz, stereo out |
| Input | 2× joystick port (Amiga standard two buttons supported) |
| Cartridge | 8 kB banked window, 1 MB address space |
| Programmable logic | 5× ATF1508AS-10JU84 CPLD (SystemVerilog, JTAG) |
| Discrete logic | 74HC series, through-hole |